research article
Analysis of Error Recovery Schemes for Networks on Chips
In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Type
research article
Web of Science ID
WOS:000231826100008
Author(s)
Theocharides, Theocharis
Vijaykrishnan, N.
Irwin, Mary Jane
Date Issued
2005
Published in
Volume
22
Issue
5
Start page
434
End page
442
Editorial or Peer reviewed
REVIEWED
Written at
OTHER
EPFL units
Available on Infoscience
November 7, 2005
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