This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18um CMOS technology, the bias current of each STSCL gate can be reduced below 10pA, which corresponds to a power-delay product (PDP) of less than 500aJ.