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  4. Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS
 
conference paper

Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS

Zografos, Odysseas
•
Sorée, Bart
•
Vaysset, Adrien
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2015
Proceedings of the 15th International IEEE Conference on Nanotechnology (NANO)
15th International IEEE Conference on Nanotechnology (NANO)

In this paper, we present a design and benchmarking methodology of Spin Wave Device (SWD) circuits based on micromagnetic modeling. SWD technology is compared against a 10nm FinFET CMOS technology, considering the key metrics of area, delay and power. We show that SWD circuits outperform the 10nm CMOS FinFET equivalents by a large margin. The area-delay-power product (ADPP) of SWD is smaller than CMOS for all benchmarks from 2.5× to 800×. On average, the area of SWD circuits is 3.5× smaller and the power consumption is two orders of magnitude lower compared to the 10nm CMOS reference circuits.

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OZ_NANO15.pdf

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