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  4. 10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS
 
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conference paper

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS

Gharibdoust, Kiarash  
•
Tajalli, Seyed Armin  
•
Leblebici, Yusuf  
2015
2015 IEEE International Solid-State Circuits Conference Digest Of Technical Papers (ISSCC)
International Solid-State Circuits Conference (ISSCC) 2015

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units and the controller is challenging for bandwidth and power reasons. Multi-tone signaling has promising characteristics for this type of interface. To keep up with the ever growing demand for higher bandwidth in multi-drop buses, we develop a 7.5Gb/s (3.75Gb/s/pin) NRZ/multi-tone (NRZ/MT) transceiver with a total link power efficiency of 1mW/Gb/s.

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Type
conference paper
DOI
10.1109/ISSCC.2015.7062985
Web of Science ID

WOS:000355252700071

Author(s)
Gharibdoust, Kiarash  
•
Tajalli, Seyed Armin  
•
Leblebici, Yusuf  
Date Issued

2015

Publisher

IEEE

Published in
2015 IEEE International Solid-State Circuits Conference Digest Of Technical Papers (ISSCC)
ISBN of the book

978-1-4799-6223-5

Total of pages

3

Start page

180

End page

181

URL

URL

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7062985
Peer reviewed

NON-REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
International Solid-State Circuits Conference (ISSCC) 2015

San Francisco, CA

February 22-26, 2015

Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/107404
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