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  4. Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems
 
conference paper

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

Burg, A.  
•
Haene, S.
•
Perels, D.
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2006
2006 Ieee International Symposium On Circuits And Systems
IEEE International Symposium on Circuits and Systems

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding.

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Type
conference paper
DOI
10.1109/ISCAS.2006.1693531
Web of Science ID

WOS:000245413504109

Author(s)
Burg, A.  
•
Haene, S.
•
Perels, D.
•
Luethi, P.
•
Felber, N.
•
Fichtner, W.
Date Issued

2006

Publisher

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

Published in
2006 Ieee International Symposium On Circuits And Systems
ISBN of the book

978-0-7803-9389-9

Start page

4102

End page

4105

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Event nameEvent placeEvent date
IEEE International Symposium on Circuits and Systems

Kos Isl, GREECE

May 21-24, 2006

Available on Infoscience
June 6, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/68377
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