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  4. Deconstructing Process Isolation
 
conference paper

Deconstructing Process Isolation

Aiken, Mark
•
Fähndrich, Manuel
•
Hawblitzel, Chris
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2006
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness

Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions. Singularity is a new operating system that uses software mechanisms to enforce process isolation. A software isolated process (SIP) is a process whose boundaries are established by language safety rules and enforced by static type checking. SIPs provide a low cost isolation mechanism that provides failure isolation and fast inter-process communication.To compare the performance of Singularity's SIPs against traditional isolation techniques, we implemented an optional hardware isolation mechanism. Protection domains are hardware-enforced address spaces, which can contain one or more SIPs. Domains can either run at the kernel's privilege level or be fully isolated from the kernel and run at the normal application privilege level. With protection domains, we can construct Singularity configurations that are similar to micro-kernel and monolithic kernel systems. We found that hardware-based isolation incurs non-trivial performance costs (up to 25--33%) and complicates system implementation. Software isolation has less than 5% overhead on these benchmarks.The lower run-time cost of SIPs makes their use feasible at a finer granularity than conventional processes. However, hardware isolation remains valuable as a defense-in-depth against potential failures in software isolation mechanisms. Singularity's ability to employ hardware isolation selectively enables careful balancing of the costs and benefits of each isolation technique.

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Type
conference paper
DOI
10.1145/1178597.1178599
Author(s)
Aiken, Mark
•
Fähndrich, Manuel
•
Hawblitzel, Chris
•
Hunt, Galen
•
Larus, James R.
Date Issued

2006

Publisher

ACM

Published in
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Start page

1

End page

10

Editorial or Peer reviewed

REVIEWED

Written at

OTHER

EPFL units
VLSC  
Available on Infoscience
December 23, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/98694
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