Several Hall sensor configurations have been integrated in CMOS 0.35 mu m technology and analyzed in terms of offset at room temperature and offset drift. We searched for the best geometry that would minimize the offset and its corresponding drift. The targeted specifications were +/- 30 mu T for offset at room temperature and +/- 0.3 mu T/degrees C for the drift. The measurement setup developed to test the Hall Effect sensors allows a clean, reliable and fast analysis of a high number of the same type of cell, located on different positions on the chip. For each structure, information about the absolute sensitivity, residual offset and its drift is obtained. An important number of chips were tested in order to also provide statistical data. Maximization of the geometrical correction factor was also performed for Hall structures with small sensing contacts in order to ensure maximum sensitivity.