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  4. Efficient ASIC implementation of a real-time depth mapping stereo vision system
 
conference paper

Efficient ASIC implementation of a real-time depth mapping stereo vision system

Moser, S.
•
Isler, O.
•
Gurkaynak, F.K.
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2003
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems
46th IEEE International Midwest Symposium on Circuits and Systems

This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo thatching and includes an occlusion detection method. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. A low-latency dataflow-oriented structure makes it possible to process 256 x 192 pixel Input streams with a rate In excess of 50 frames per second, amounting to more than 54 million pixel x disparity measurements per second (PDS) (for a 25-pixel disparity range), or roughly 18 GOPS. The design has been Integrated In a 0.25 mu m standard CMOS technology and occupies an area of less than 3 mm(2).

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Type
conference paper
DOI
10.1109/MWSCAS.2003.1562575
Web of Science ID

WOS:000234964300360

Author(s)
Moser, S.
•
Isler, O.
•
Gurkaynak, F.K.
•
Burg, A.  
•
Felber, N.
•
Kaeslin, H.
•
Fichtner, W.
•
Kuhn, M.
Date Issued

2003

Publisher

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

Published in
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems
ISBN of the book

0-7803-8294-3

Start page

1478

End page

1481

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Event nameEvent placeEvent date
46th IEEE International Midwest Symposium on Circuits and Systems

Cairo, EGYPT

Dec 27-30, 2003

Available on Infoscience
June 6, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/68359
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