Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors
 
research article

Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors

Beckers, Arnout  
•
Thewissen, Maarten
•
Soree, Bart
October 14, 2018
Journal Of Applied Physics

This paper investigates energy filtering in silicon nanowires and nanosheets by resonant electron tunneling through a geometric superlattice. A geometric superlattice is any kind of periodic geometric feature along the transport direction of the nanowire or nanosheet. Multivalley quantum-transport simulations are used to demonstrate the manifestation of minibands and minibandgaps in the transmission spectra of such a superlattice. We find that the presence of different valleys in the conduction band of silicon favors a nanowire with a rectangular cross section for effective energy filtering. The obtained energy filter can consequently be used in the source extension of a field-effect transistor to prevent high-energy electrons from contributing to the leakage current. Self-consistent Schrodinger-Poisson simulations in the ballistic limit show minimum subthreshold swings of 6 mV/decade for geometric superlattices with indentations. The obtained theoretical performance metrics for the simulated devices are compared with conventional III-V superlatticeFETs and TunnelFETs. The adaptation of the quantum transmitting boundary method to the finite-element simulation of 3-D structures with anisotropic effective mass is presented in Appendixes A and B. Our results bare relevance in the search for steep-slope transistor alternatives which are compatible with the silicon industry and can overcome the power-consumption bottleneck inherent to standard CMOS technologies. Published by AIP Publishing.

  • Details
  • Metrics
Type
research article
DOI
10.1063/1.5043543
Web of Science ID

WOS:000447148100011

Author(s)
Beckers, Arnout  
Thewissen, Maarten
Soree, Bart
Date Issued

2018-10-14

Publisher

AMER INST PHYSICS

Published in
Journal Of Applied Physics
Volume

124

Issue

14

Article Number

144304

Subjects

Physics, Applied

•

Physics

•

field-effect transistors

•

quantum

•

transport

•

devices

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ICLAB  
Available on Infoscience
December 13, 2018
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/152892
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés