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doctoral thesis

MOS current-mode logic standard cells for high-speed low-noise applications

Badel, Stéphane
2008

With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integrated circuit is inevitably transmitted to the analog parts, through the power supply networks and through the common silicon substrate. Therefore, in the past years a lot of attention has been drawn to alternative digital logic circuit styles that are more friendly than classical CMOS in a mixed-signal environment. MOS Current-Mode Logic (MCML) is a differential logic circuit style that provides high-speed operation together with low generation of supply noise, and is thus a natural candidate for implementing digital blocks in mixed-signal circuits. In this work, MOS Current-Mode Logic circuits are studied, with a focus on the implementation of standard-cell based digital circuits. To this aim, a design methodology is proposed to build efficient MCML standard-cell libraries, and a complete top-down design flow allowing the construction of complex digital circuits with differential standard-cells is proposed. The results of implementing a digital encoder block for analog-to-digital applications are presented.

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Type
doctoral thesis
DOI
10.5075/epfl-thesis-4098
Author(s)
Badel, Stéphane
Advisors
Leblebici, Yusuf  
Date Issued

2008

Publisher

EPFL

Publisher place

Lausanne

Thesis number

4098

Total of pages

211

Subjects

low-noise circuits

•

current-mode circuits

•

differential circuits

•

standard-cell library

•

design automation

•

circuits à bas bruit

•

logique en mode courant

•

circuits différentiels

•

bibliothèque de cellules standard

•

conception automatisée

EPFL units
LSM  
Faculty
STI  
School
IEL  
Doctoral School
EDMI  
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/22554
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