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  4. Power Efficient Hardware Implementation of a Fuzzy Neural Network
 
conference paper

Power Efficient Hardware Implementation of a Fuzzy Neural Network

Dlugosz, Rafal Tomasz  
•
Pedrycz, Witold
•
Kolodyazhniy, Vitaliy
2010
Proceedings of the 17th International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES)
17th International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES)

This paper presents a digital, transistor level implemented neo-fuzzy neural network. This type of neural network is particularly well suited for real-time applications like those encountered in signal processing and nonlinear system identification. We consider in detail a flexible reconfigurable circuit of a single nonlinear synapse of this network. When combining such circuits, single-layer or multilayer networks can be designed. The advantages of the proposed circuit come in the form of reduced redundancy, high data rate due to parallel operation, low power consumption, and an overall flexibility of system configuration.

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Type
conference paper
Author(s)
Dlugosz, Rafal Tomasz  
Pedrycz, Witold
Kolodyazhniy, Vitaliy
Date Issued

2010

Publisher

Technical University of Lodz

Published in
Proceedings of the 17th International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES)
Start page

576

End page

580

Subjects

fuzzy neural networks

•

parallel operation

•

CMOS realization

•

low energy consumption

•

digital circuits

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESPLAB  
Event nameEvent placeEvent date
17th International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES)

Wroclaw, Poland

June 24-26, 2010

Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/64282
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