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  4. Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing
 
conference paper

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Nikolic, Stefan  
•
Zgheib, Grace  
•
Ienne, Paolo  
January 1, 2020
2020 Acm/Sigda International Symposium On Field-Programmable Gate Arrays (Fpga '20)
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both within and across multiple clusters, can eschew the transistor delays of crossbars, connection blocks, and switch blocks. In this paper we investigate the usefulness of enhancing classical Field-Programmable Gate Array (FPGA) architectures with direct connections between LUTs. We present an efficient algorithm for searching automatically the most interesting patterns of such direct connections. Despite our methods being fairly conservative and relying on the use of unmodified standard CAD tools, we obtain a 2.77% improvement of the geometric mean critical path delay of a standard benchmark set, with improvement ranging from -0.17% to 7.3% for individual circuits. As modest as these results may seem at first glance, we believe that they position direct connections between LUTs as a promising topic for future research. Extending this work with dedicated CAD algorithms and exploiting the increased possibilities for optimal buffering, diagonal routing, and pipelining could prove direct connections important to the continuation of performance improvement into next generation FPGAs.

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Type
conference paper
DOI
10.1145/3373087.3375315
Web of Science ID

WOS:000693956500022

Author(s)
Nikolic, Stefan  
Zgheib, Grace  
Ienne, Paolo  
Date Issued

2020-01-01

Publisher

ASSOC COMPUTING MACHINERY

Publisher place

New York

Published in
2020 Acm/Sigda International Symposium On Field-Programmable Gate Arrays (Fpga '20)
ISBN of the book

978-1-4503-7099-8

Start page

150

End page

160

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Event nameEvent placeEvent date
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

Seaside, CA

Feb 23-25, 2020

Available on Infoscience
September 25, 2021
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/181650
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