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  4. Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs
 
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conference paper

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Tajalli, Armin  
•
Muller, Paul  
•
Atarodi, Mojtaba
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2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS)
International Symposium on Circuits and Systems (ISCAS)

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition to its acceptable FTOL and flexible topology, have made it very suitable for short-haul multi-rate applications.

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Type
conference paper
DOI
10.1109/ISCAS.2006.1693033
Author(s)
Tajalli, Armin  
•
Muller, Paul  
•
Atarodi, Mojtaba
•
Leblebici, Yusuf  
Date Issued

2006

Publisher

IEEE

Published in
Proceedings of the International Symposium on Circuits and Systems (ISCAS)
Start page

2109

End page

2112

Subjects

CMOS Integrated circuits

•

Clock and data recovery

•

Jitter tolerance

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
International Symposium on Circuits and Systems (ISCAS)

Kos, Greece

May 21-24

Available on Infoscience
June 21, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/9174
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