The field of application of Phasor Measurement Units (PMUs) might be limited by the PMU measurements reporting latencies and achievable reporting rates, particularly with respect to power system protection applications that typically require very low latencies. A way to speed-up synchrophasor estimation algorithms based on the use of the Discrete Fourier Transform (DFT) refers to the usage of stable and accurate recursive processes for the DFT estimation. In this respect, this paper presents a synchrophasor estimation algorithm, called Interpolated-Modulated Sliding DFT (IpMSDFT), characterized by high accuracies and reduced latencies, enabling reporting rates up to thousands of synchrophasor per second. It is composed by two stages: (i) a guaranteed-stable technique for sample-by-sample DFT computation; (ii) an enhanced version of the classical IpDFT algorithm for synchrophasor estimation. The algorithm is analytically formulated and its digital design tailored to allow a feasible deployment on an FPGA-based PMU. The IpMSDFT-based PMU is finally validated with respect to the numerical stability of the proposed solution, its reporting latencies and the achievable reporting rates.