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  4. Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs
 
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conference paper

Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs

De Michielis, L.  
•
Moselund, K. E.  
•
Bouvet, D.  
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2009
International Symposium on VLSI Technology, Systems, and Applications, Proceedings
International Symposium on VLSI Technology, Systems and Applications

We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa's and average values of hundreds of MPa's. ©2009 IEEE.

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Type
conference paper
DOI
10.1109/VTSA.2009.5159319
Web of Science ID

WOS:000272451000053

Author(s)
De Michielis, L.  
•
Moselund, K. E.  
•
Bouvet, D.  
•
Dobrosz, P.
•
Olsen, S.
•
O'Neill, A.
•
Lattanzio, L.  
•
Najmzadeh, M.  
•
Selmi, L.
•
Ionescu, A. M.  
Date Issued

2009

Publisher

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

Published in
International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Start page

119

End page

120

Subjects

Mobility

•

Silicon

•

Stress

Peer reviewed

NON-REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Event nameEvent placeEvent date
International Symposium on VLSI Technology, Systems and Applications

Hsinchu, TAIWAN

Apr 27-29, 2009

Available on Infoscience
November 8, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/57225
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