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patent

Reconfigurable logic circuit

Mentens, Nele
•
Regazzoni, Francesco
•
Charbon, Edoardo  
2020

The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, - a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit, - a fourth, fifth and sixth switching circuit arranged for receiving a fourth input bit, a fifth input bit and a sixth input bit and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, - a first, second and third AND logic block, each arranged for receiving a different pair of the outputs of said fourth, fifth and sixth switching circuit, - a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit.

  • Details
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Type
patent
EPO Family ID

60805441

Author(s)
Mentens, Nele
•
Regazzoni, Francesco
•
Charbon, Edoardo  
Note

Alternative title(s) : (de) Rekonfigurierbare logikschaltung (fr) Circuit logique reconfigurable

TTO classification

TTO:6.1767

EPFL units
AVP-R-TTO  
AQUA  
DOICountry codeKind codeDate issued

EP3714545

EP

B1

2023-01-04

US11309896

US

B2

2022-04-19

US2020366294

US

A1

2020-11-19

EP3714545

EP

A1

2020-09-30

WO2019101660

WO

A1

2019-05-31

GB201719355

GB

D0

2018-01-03

Available on Infoscience
October 5, 2020
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/172225
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