Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot

• Presented at: NASA/DoD Conference on Evolvable Hardware (EH'2003), Chicago, Illinois, USA, July 9-11
• Published in: NASA/DoD Conference on Evolvable Hardware (EH'2003), p. 189-198
• Publication date: 2003

A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.

Note: Lohn, J. and Zebulum, R. and Steincamp, J. and Keymeulen, D. and Stoica, A. and Ferguson, M. I. (eds.)

Keywords: POEtic

Reference

• LIS-CONF-2003-006

• URL: http://ic.arc.nasa.gov/projects/eh2003/

Record created on 2006-01-12, modified on 2012-03-20