A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

• Presented at: 31st European Solid-State Circuits Conference ESSCIRC, Grenoble, France, September 12-16
• Published in: Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC), p. 193-196
• : , 2005

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18µm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045µm2 silicon area.

Keywords: clock recovery ; CDR ; clock and data recovery ; gated oscillator ; top-down design ; design methodology

Reference

• LSM-CONF-2005-024
• doi:10.1109/ESSCIR.2005.1541592

• URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=1541592&isnumber=32889&punumber=10265&k2dockey=1541592@ieeecnfs&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=13&access=no

Record created on 2005-12-06, modified on 2012-03-20