Hybrid CMOS-SET devices and circuits: modeling, simulation and design

The quickening pace of the MOSFET technology scaling has pushed the MOSFET dimension towards 10 nanometer channel length, where it is going to face the following fundamental and performance limiting factors: (i) electrostatic limits, (ii) source to drain tunneling, (iii) carrier mobility, (iv) process variations and (v) static leakage. Although many new techniques (e.g., SOI, double gate, metal gate, high-k dielectric, strained Si etc.) can provide MOSFET technology some more lifetimes, they do not solve those key problems of the sub 10nm devices. Therefore in near future CMOS has to share its domination on modern ICs with fundamentally new nano-technologies such as Single Electron Transistor (SET). SETs are now becoming attractive candidates of post-CMOS VLSI mainly due to its (i) nano feature size (ii) ultra low power density and (iii) unique Coulomb blockade oscillations effect. Although CMOS and SET are quite complementary to each other (in terms of power dissipation, current driving capability etc.), combination of CMOS and SET device characteristics can bring out new functionalities, which are un-mirrored to pure CMOS technology. Therefore, a detailed investigation of the behavior and fabrication of SET devices and SET based circuits is absolutely necessary for its successful implementation in future VLSI. The main objectives of this Ph.D. thesis can be divided into three parts: (i) Developing compact analytical models for SET (ii) Building CMOS-SET co-simulation environment by using those compact models, and, (iii) Novel CMOS-SET hybrid circuit design with the help of that co-simulation environment. A compact analytical model (named MIB) for SET device, which is applicable for wide-range of temperature and drain to source voltage and valid for single/multiple gate symmetric/asymmetric device, is developed in this work. MIB model can be used for both digital and analog SET circuit design and for both pure SET and hybrid CMOS-SET circuit simulation. The performance factors (power dissipation, delay etc.) of SET logic are also analyzed by using the MIB model. The MIB model is then implemented in Smartspice circuit simulator (from SILVACO International) through its Verilog-A interface in order to develop a CAD framework for CMOS-SET co-simulation. The accuracy of the MIB model and its CMOS-SET co-simulation framework has been verified with different benchmarked hybrid CMOS-SET architectures. Using this CAD framework, a novel CMOS-SET hybrid device (called SETMOS) is designed, which offers Coulomb Blockade oscillation at much higher current level than the traditional SETs. Moreover, SETMOS exhibits a unique quasi-periodic negative differential resistance characteristics and multi-level hysteresis behavior that could be attractive for Multiple Valued (MV) circuit design. Using SETMOS device, different building blocks of Quaternary logic (e.g., literal gate, Transmission-gate etc.) and Quaternary SRAM cell has been designed and fully verified by analytical simulations.

Thèse École polytechnique fédérale de Lausanne EPFL, n° 3190 (2005)
Section de génie électrique et électronique
Faculté des sciences et techniques de l'ingénieur
Institut de microélectronique et microsystèmes
Laboratoire d'électronique générale 2
Jury: Jacques Gautier, Yusuf Leblebici, Juan Ramon Mosig, Christoph Wasshuber

Public defense: 2005-2-10


Published as Hybrid CMOS single-electron-transistor device and circuit design (Artech House, 2006, ISBN 1-59693-069-1)


Record created on 2005-03-16, modified on 2013-10-02