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  4. Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices
 
research article

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Kamaei, Sadegh  
•
Liu, Xia  
•
Saeidi, Ali  
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August 31, 2023
Nature Electronics

The co-integration of logic switches and neuromorphic functions could be used to create new computing architectures with low power consumption and novel functionalities. Two-dimensional (2D) semiconductors and ferroelectric materials could be potentially used to make such devices, but integrating them on the same platform is challenging. Here we show that the 2D semiconductor tungsten diselenide and 2D/2D heterostructures of tungsten diselenide/tin diselenide can be integrated with doped high-k ferroelectric (silicon-doped hafnium oxide) and high-k dielectric gate stacks. With this single platform, four types of logic switch-2D metal-oxide-semiconductor field-effect transistors (FETs), 2D/2D tunnel FETs, negative-capacitance 2D FETs and negative-capacitance 2D/2D tunnel FETs-can be created. The negative-capacitance tungsten diselenide/tin diselenide tunnel FET exhibits an average subthreshold swing of 55 mV dec-1 over four decades of current, and the negative-capacitance tungsten diselenide FET exhibits an average subthreshold swing of 50 mV dec-1 over three decades. The shared ferroelectric gate stacks on 2D devices can also be exploited to create co-integrated artificial synapses for neuromorphic computing.

A platform that integrates a ferroelectric gate and two-dimensional heterostructure of tungsten diselenide and tin diselenide can operate in various gating modes, demonstrating typical transistor, steep-slope transistor and synaptic behaviours.

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Type
research article
DOI
10.1038/s41928-023-01018-7
Web of Science ID

WOS:001061975800002

Author(s)
Kamaei, Sadegh  
Liu, Xia  
Saeidi, Ali  
Wei, Yingfen  
Gastaldi, Carlotta  
Brugger, Juergen  
Ionescu, Adrian M.  
Date Issued

2023-08-31

Publisher

NATURE PORTFOLIO

Published in
Nature Electronics
Subjects

Engineering, Electrical & Electronic

•

Engineering

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negative-capacitance

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next-generation

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transistor

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inverters

•

circuits

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fet

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

Available on Infoscience
October 9, 2023
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/201430
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