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  4. Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs
 
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conference paper

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu, Minghua  
•
Matioli, Elison
May 13, 2018
Proceedings of the IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300 C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and high output noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.

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M.Zhu and E. Matioli, ISPSD 2018_chicago.pdf

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