Infoscience

Conference paper

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS transistors followed by 1:4 demux stages are used to sample the signal. Skew and gain adjustment is implemented on-chip. The ADC consumes 667mW at 90GS/s and 845mW at 100GS/s and can be operated from a single supply voltage. It is implemented in 32nm SOI CMOS and occupies 0.45mm2.

Keywords: SAR ; ADC ; time-interleaved ; SOI ; CMOS

Reference

  • EPFL-CONF-190728

Record created on 2013-11-26, modified on 2013-12-17

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