Networks on Chips: from Research to Products

• Presented at: 47th Design Automation Conference (DAC 2010), Anaheim, USA, June 13-18, 2010
• Published in: Proceedings of the 47th Design Automation Conference (DAC 2010), vol. 1, p. 300-305
• Publication date: 2010

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.

Keywords: Network on Chip SoC ; NoC ; System on Chip

Reference

• EPFL-CONF-149700

Record created on 2010-06-25, modified on 2012-03-20