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Conference paper

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

Sacchetto, D.; Ben Jamaa, M. H.; De Micheli, G.; Leblebici, Y.
  • Presented at: 39th European Solid-State Device Research Conference (ESSDERC), Athens, Greece, September 14-18
  • Published in: Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
  • Publication date: 2009

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior.

Keywords: nanowire ; FET ; multichannel ; ambipolar ; vertical integration

Reference

  • EPFL-CONF-141935

Record created on 2009-10-15, modified on 2012-03-27

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