Guerraoui, Rachid ; Henzinger, Thomas A. ; Singh, Vasu

Presented at: 21st International Conference on Computer Aided Verification, Grenoble, June 26 - July 2, 2009.

Accepted in: Proceedings of the 21st International Conference on Computer Aided Verification, 2009

Berlin: Springer, 2009.

Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed memory models, with the atomicity of operations as provided by the hardware. This paper presents the first approach to verify STMs under relaxed memory models with atomicity of 32 bit loads and stores, and read-modify-write operations. We present RML, a new high-level language for expressing concurrent algorithms with a hardware-level atomicity of instructions, and whose semantics is parametrized by various relaxed memory models. We then present our tool, FOIL, which takes as input the RML description of an STM algorithm and the description of a memory model, and automatically determines the locations of fences, which if inserted, ensure the correctness of the STM algorithm under the given memory model. We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order.

Keyword(s): Transactional memories, Relaxed memory models, Model checking

Reference: MTC-CONF-2009-002

URL: http://www-cav2009.imag.fr/