Improving the power-delay performance in subthreshold source-coupled logic circuits

• Presented at: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 10-12
• Published in: Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), p. 21-30. Svensson, Lars ; Monteiro, Jose (eds.)
• Series: Integrated Circuit and System Design
• Portugal: Springer, 2008

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

Keywords: Source-coupled logic (SCL) ; Current-mode logic (CML) ; Subthreshold ; Weak inversion ; Subthreshold SCL

Reference

• LSM-CONF-2008-035
• View record in Web of Science

• URL: http://algos.inesc-id.pt/patmos/home.shtml?general

Record created on 2008-07-10, modified on 2012-03-29