Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

• Published in: IEE Electronics Letters, vol. 43, num. 17, p. 911-913
• Publication date: 2007

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can be utilized successfully for bias currents as low as 1 nA, achieving sufficiently high gain (>3) over a wide frequency range.

Keywords: CMOS integrated circuit design ; Source coupled logic ; Ultra low power ; Digital circuits ; Subthreshold source-coupled logic ; SCL ; STSCL ; Current-mode loigc ; CML ; CMOS integrated circuts

Reference

• LSM-ARTICLE-2007-002
• doi:10.1049/el:20071208
• View record in Web of Science

• URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4293090&isnumber=4293085&punumber=2220&k2dockey=4293090@ieejrns&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=9&access=no

Record created on 2007-07-25, modified on 2012-03-21