A Power-Efficient LVDS Driver Circuit in 0.18-um CMOS Technology

• Presented at: IEEE 3rd Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), Bordeaux, July 2-5
• Published in: Proceedings of 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), p. 145-148
• Bordeaux: , 2007

This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent input capacitance of 50 fF. Designed in 0.18 μm CMOS technology, the entire output driver circuit including the input pre-driver, draws only 5.6 mArms while the output voltage swing is VOD = 400 mV and the other specs are compliant with the LVDS requirements.

Keywords: CMOS integrated circuits ; LVDS output driver ; Low power ; Output driver ; Output buffer

Reference

• LSM-CONF-2007-010

• URL: http://prime07.ixl.fr/

Record created on 2007-06-21, modified on 2012-03-20